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rev. 1.0 3/14 copyright ? 2014 by silicon laboratories SI51218 SI51218 t hree o utputs f actory p rogrammable c lock g enerator features applications description the factory programmable SI51218 is a low power, small footprint and frequency flexible programmable clock generator targeting low power, low cost and high volume consumer and embedded applications. the device operates from a single crystal or an external clock source and generates up to 3 clock outputs from 32.768 khz to 200 mhz. they are factory programmed to provide customized output frequencies, control inputs and ac parameter tuning like output driv e strength that are optimized for customer board condition and app lication requirements. a separate vddo supply pin supports clock outputs at a different voltage level. functional block diagram ? generates up to 3 lvcmos clock outputs from 32.768 khz to 200 mhz ? accepts crystal or reference clock input ?? 3 to 166 mhz reference clock input ?? 8 to 48 mhz crystal input ? programmable fsel, pd and oe input functions ? low power dissipation ? separate voltage supply pins ?? v dd = 2.5 to 3.3 v ?? v ddo = 1.8 to 3.3 v (v ddo v dd ) ? low cycle-cycle jitter ? programmable output rise and fall times ? ultra small 8-pin tdfn package (1.4 mm x 1.6 mm) ? operation temperature: 0?70 ? c ? crystal / xo replacement ? digital media players ? portable devices ? dtv/iptv pll with modulation control 4 programmable configuration register 2 clkout1/ refout1 (vdd) oe/ fsel xi n/ clki n xout vss vddo buffers, di vi ders and switch mat r i x 6 clkout2/ refout2(vddo) oe/fsel/pd# 7 clkout3(vddo) 8 5 v-reg to core to pin 6/7 clock drivers vdd 1 to pin 4 clock driver and oscillator 3 patents pending ordering information: see page 10. pin assignments 1 2 3 45 6 7 8 vdd xout xin/clkin clkout1/refout1 ? fsel/oe vss clkout2/refout2 ? fsel/oe/pd# clkout3 vddo SI51218
SI51218 2 rev. 1.0
SI51218 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. input frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.2. output frequency range and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3. frequency select (fsel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4. power down (pd ) or output enable (oe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4. pin descriptions?8-pin tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 5. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 6. package outline: 8-pin tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. pcb land pattern: 8-pin tdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
SI51218 4 rev. 1.0 1. electrical specifications table 1. dc electrical specifications (v dd =3.3 v 10% or v dd =2.5 v 5%, t a =0 to 70 o c) parameter symbol test condition min typ max unit operating voltage v dd v dd =3.3 v 10% 2.97 3.3 3.63 v v dd =2.5 v 5% 2.375 2.5 2.625 v v ddo v ddo v dd 1.71 ? 3.6 v output high voltage v oh i oh =?4ma, v ddx =v dd or v ddo v ddx -0.5 ? ? v output low voltage v ol i ol =4ma, ? ? 0.3 v input high voltage v ih cmos level 0.7 v dd ??v input low voltage v il cmos level ? ? 0.3 v dd v operating supply current i dd f in =20 mhz, clk- out1=32.768khz, refout2=20 mhz clk- out3=26mhz, c l =0, v dd =v ddo =3.3 v ?6?ma nominal output impedance z o ?30? ? internal pull-up/pull-down resistor r pup /r pd pin 6 ? 150k ? ? input pin capacitance c in input pin capacitance ? 3 5 pf load capacitance c l clock outputs < 166 mhz ? ? 15 pf clock outputs > 166 mhz ? ? 10 pf
SI51218 rev. 1.0 5 table 2. ac electrical specifications (v dd =3.3 v 10% or v dd =2.5 v 5%, t a =0 to 70 o c) parameter symbol test condition min typ max unit input frequency range f in1 crystal input 8 ? 48 mhz input frequency range f in2 reference clock input 3 ? 166 mhz output frequency range f out 0.032768 ? 200 mhz frequency accuracy f acc configuration dependent ? 0 ? ppm output duty cycle dc out measured at v dd/2 45 50 55 % input duty cycle dc in clkin, clkout through pll 30 50 70 % output rise time t r clkout1/2/3 in mhz range c l =15 pf, 20 to 80% ?13.0ns output fall time t f clkout1/2/3 in mhz range c l =15 pf, 20 to 80% ?13.0ns period jitter pj 1 clkout1/2/3 in mhz range, v dd =v ddo =3.3 v, cl=15 pf ?150 * ?ps period jitter pj 2 clkout1/3 at 32.768khz, v dd =v ddo =3.3 v, cl=15 pf ? 1500 * ?ps cycle-to-cycle jitter ccj cl kout1/2/3, in mhz range v dd =v ddo =3.3 v, cl=15 pf ?100 * ?ps power-up time t pu time from 0.9 v dd to valid fre- quencies at all clock outputs ?1.25.0ms output enable time t oe time from oe raising edge to active at outputs (asynchronous) ?15?ns output disable time t od time from oe falling edge to active at outputs (asynchronous) ?15?ns *note: jitter performance depends on configuration and programming parameters.
SI51218 6 rev. 1.0 table 3. absolute maximum conditions parameter symbol test condition min typ max unit main supply voltage v dd_3.3v ?0.5 ? 4.2 v input voltage v in relative to v ss ?0.5 ? v dd +0.5 v temperature, storage t s non-functional ?65 ? 150 c temperature, operating ambient t a functional, c-grade 0 ? 70 c temperature, junction t j functional, power is applied ?? 125c temperature, soldering t sol non-functional ? ? 260 c esd protection (human body model) esd hbm jedec (jesd 22 - a114) ?4000 ? 4000 v esd protection (charge device model) esd cdm jedec (jesd 22 - c101) ?1500 ? 1500 v esd protection (machine model) esd mm jedec (jesd 22 - a115) ?200 ? 200 v note: while using multiple power supplies, the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required . table 4. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 170.8 c/w thermal resistance junction to case ? jc still air 98.8 c/w
SI51218 rev. 1.0 7 2. design considerations 2.1. typical appl ication schematic 2.2. comments and recommendations decoupling capacitor: a decoupling capacitor of 0.1 f must be used between vdd and vss on the pins 1 and 8. place the capacitor on the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible do not use vias between the decoupling capacitor and the vdd pin. in addition , a 10 f capacitor should be placed between vdd and vss. crystal and crystal load: only use a parallel resonant fundamental at cut crystal. do not use higher overtone crystals. to meet the crystal initial ac curacy specification (in ppm) make sure that external crystal load capacitor is matched to crystal load specification. to determi ne the value of cl1 and cl2, use the following formula: cl1 = cl2 = 2cl ? (cpin + cp) where: cl is load capacitance stated by crystal manufacturer cpin is the SI51218 pin capacitance (4pf) cp is the parasitic capacitance of the pcb traces. example: if a crystal with cl=12 pf specificat ion is used and cp=1 pf (parasit ic pcb capacitance on pcb), 19 pf external capacitors from pi ns xin (pin 3) and xout (p in 2) to vss are required. us ers must verify cp value. dotted line shows the optional termination resistors vdd xout xin clkout1 clkout2 vddo clkout3 SI51218 0.1 f vdd 10f cl1 cl2 vss 0.1 f
SI51218 8 rev. 1.0 3. functional description 3.1. input frequency range the input frequency range is from 8.0 to 48.0 mhz for crysta ls and ceramic resonators. if an external clock is used, the input frequency range is from 8.0 to 166.0 mhz. 3.2. output freque ncy range and outputs up to three outputs can be programmed as clkout or refout. clkout output can be synthesized to frequency value from 32.768 khz to 20 0 mhz. refout is the buffered output of the oscillator and is the same frequency as the input frequency. refout2 (pin6) frequency can also be programmed to input frequency divided by 2 to 32. by using only low cost, fundamental mode crystals, the SI51218 can syn thesize output frequency up to 200 mhz, eliminating the need for higher order crystals (xtals) and crystal oscillators (xos). the 32.768 khz output can replace the 32.768 khz crystal which is widely used in many embedded an d mobile systems. this reduces the cost while improving the system clock accuracy, perf ormance, and reliability. 3.3. frequency select (fsel) the SI51218 pin 4 and 6 can be programmed as frequency select input (fsel). if fsel function is used, one output pin can switch between two predefined frequencies by fsel input. the set of frequencies in table 5 is given as an example. 3.4. power down (pd ) or output enable (oe) the SI51218 pin 6 can be programmed as pd input. pin 4 and pin 6 can be programmed as oe input. pd turns off both pll and output buffers whereas oe on ly disables the output buffers to hi-z . table 5. example frequencies fsel (pin 6) clkout3 (pin 7) 066mhz 133mhz
SI51218 rev. 1.0 9 4. pin descriptions?8-pin tdfn table 6. SI51218 pin descriptions pin # name type description 1 vdd pwr 2.5 to 3.3 v power supply. 2 xout o crystal output. leave this pin unconn ected (floating) if an external clock input is used. 3 xin/clkin i external crystal and clock input. 4 clkout1/refout1/ fsel/oe i/o programmable clkout1 or refout1 output or multifunction control input. the frequency at this pin is synthesized by internal pll if pro- grammed as clkout1. if programmed as refout1, output clock is buffered output of crystal or reference clock input. if programmed as multifunction control input, it can be fsel and oe. 5 vss gnd ground. 6 clkout2/refout2/ fsel/oe/pd i/o programmable clkout2 or refout2 output or multifunction control input. the frequency at this pin is synthesized by internal pll if pro- grammed as clkout2. if programmed as refout2, output clock is buffered output of crystal or reference clock input. if programmed as multifunction control input, it can be fsel,oe and pd . it is power by vddo (pin 8). 7 clkout3 o programmable clkout3 output. the frequency at this pin is synthe- sized by internal pll. it is power by vddo (pin 8). 8 vddo pwr 1.8 to 3.3 v output power supply to clkout2/3 (pin6/7). 1 2 3 45 6 7 8 vdd xout xin/clkin clkout1/refout1 ? fsel/oe vss clkout2/refout2 ? fsel/oe/pd# clkout3 vddo SI51218
SI51218 10 rev. 1.0 5. ordering information part number package type temperature SI51218-axxxfm 8-pin tdfn commercial, 0 to 70 ? c SI51218-axxxfmr 8-pin tdfn?tape and reel co mmercial, 0 to 70 ? c si 52112 bx gm2r base part number SI51218 axxx fmr base part number a = product revision a xxx = 2 nd option code a three character code will be assigned for each configuration f = 0 to +70c (operating temp range) m = tdfn, rohs6, pb free r = tape & reel; (b lank) = canister
SI51218 rev. 1.0 11 6. package outline: 8-pin tdfn figure 1. 8-pin tdfn package table 7. package diagram dimensions dimension min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref. b 0.15 0.20 0.25 d1.60 bsc d2 1.00 1.05 1.10 e0.40 bsc e1.40 bsc e2 0.20 0.25 0.30 l 0.30 0.35 0.40 aaa 0.10 bbb 0.10 ccc 0.10 ddd 0.07 eee 0.08 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
SI51218 12 rev. 1.0 7. pcb land pattern: 8-pin tdfn figure 2. 8-pin tdfn land pattern table 8. pcb land pattern dimensions (mm) dimension mm c1.40 e0.40 x1 0.75 y1 0.20 x2 0.25 y2 1.10 ?
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